A. Field of the Invention
This invention relates to the field of digital data processing systems wherein one or more host data processors utilize one or more supporting scientific processors in conjunction with storage systems that are commonly accessible. More particularly it relates to an improved High Performance Storage Unit for use in such a digital data processing system. Still more particularly this invention relates to an improved multiple port memory system having port decode error detecting circuitry. Still more particularly, the invention relates to a multiple port memory system operable in a pipeline mode and having error detection circuitry for signaling the occurrence of decoding errors as they are detected.
B. State of the Prior Art
Digital data processing systems are known wherein one or more independently operable data processors function with one or more commonly accessible main storage systems. Systems are also known that utilize a support processor with its associated dedicated supporting, or secondary storage system. Such support processors are often configured to perform specialized scientific computations and are commonly under task assignment control of one of the independently operable data processors. The controlling data processor is commonly referred to as a "host processor". The host processor characteristically functions to cause a task to be assigned to the support processor, to cause required instructions and data to be transferred to the secondary storage system; to cause the task execution to be initiated; and to respond to signals indicating the task has been completed, so that results can be transferred to the selected main storage systems. It is also the duty of the host processor to recognize and accommodate conflicts in usage and timing that might be detected to exist. Commonly, the host processor is free to perform other data processing matters while the support processor is performing its assigned tasks. It is also common for the host processor to respond to intermediate needs of the support processor, such as providing additional data if required, responding to detected fault conditions and the like.
In the past, support scientific data processors have been associated with host data processing systems. One such prior art scientific processor is disclosed in U.S. Pat. No. 4,101,960, entitled "Scientific Processor" and assigned to Burroughs Corporation, of Detroit, Mich. In that system, a single instruction multiple data processor, which is particularly suited for scientific applications, includes a high level language programmable front-end processor; a parallel task processor with an array memory; a large high speed secondary storage system having a multiplicity of high speed input/output channels commonly coupled to the front-end processor and to the array memory; and an over-all control unit. In operation of that system, an entire task is transferred from the front-end processor to the secondary storage system whereupon the task is thereafter executed on the parallel task processor under the supervision of the control unit, thereby freeing the front-end processor to perform general purpose input/output operations and other tasks. Upon parallel task completion, the complete results are transferred back to the front-end processor from the secondary storage system.
It is believed readily seen that the front-end processor used in this earlier system is a large general purpose data processing system which has its own primary storage system. It is from this primary storage system that the entire task is transferred to the secondary storage system. Further, it is believed to be apparent that an input/output path exists to and from the secondary storage system from this front-end processor. Since task transfers involve the use of the input/output path of the front-end processor, it is this input/output path and the transfer of data thereon between the primary and secondary storage systems which becomes the limiting link between the systems. Such a limitation is not unique to the Scientific Processor as disclosed in U.S. Pat. No. 4,101,960. Rather, this input/output path and the transfers of data are generally considered to be the bottleneck in many such earlier known systems.
The present scientific data processing system is considered to overcome the data transfer bottleneck by providing an unique system architecture using a high speed memory unit which is commonly accessible by the host processor and the scientific processor. Further, when multiple high speed storage units are required, a multiple unit adapter is coupled between a plurality of high speed memory units and the scientific processor.
Data processing systems are becoming more and more complex. With the advent of integrated circuit fabrication technology, the cost per gate of logic elements is greatly reduced and the number of gates utilized is ever-increasing. A primary goal in architectural design is to improve the through-put of problem solutions. Such architectures often utilize a plurality of processing units in cooperation with one or more multiple port memory systems, whereby portions of the same problem solution may be parcelled out to different processors or different problems may be in the process of solution simultaneously.
Another primary goal in the development of data processing systems is to provide ever-increasing assurance of the integrity of the data being manipulated. Early data processing systems were designed to provide indication, for example by interrupt, of detected data errors. The use of parity bits on data words or data characters is will known. It was and still is a primary means of establishing that an error condition exists in an associated data word or character. Normally, upon detection of a parity error, the erroneous data word was inhibited from further use in the data processing run stream, and an indication of parity fault was provided so that maintenance could be performed on the system. It is, of course, apparent that multiple errors can be offsetting, and thereby defeat the parity checking circuitry. Such offsetting errors may allow erroneous data to be processed.
It has long been recognized to be advantageous in the transmission of binary digital signals to encode these signals in an error detecting/correcting code format that allows the detection of errors at the receiving end. The detection of errors is coupled with the correction of predetermined numbers of errors when decoded. This type of transmission pays the price of transmitting more bits than incorporated in the data bits, but gains the advantage of assuring that the received data is accurate or is to some degree correctable. Such a technique was proposed for coding data permitting correction of single bit errors and detection of double bit errors, by R. W. Hamming in an article, entitled "Error Detecting and Error Correcting Codes" in the Bell System Technical Journal, Volume 29, Pages 147 through 160, published April, 1950. This type of approach found early adaptation in data communications, and more recently has been applied to memory systems. Considerable effort has been devoted to such fault tolerant memory systems, relating to detecting and correcting various combinations of error conditions, all incorporating the use of Error Correction Codes (ECC). For example, ECC systems are described in U.S. Pat. No. 3,755,770 to Donald Walter Price; U.S. Pat. No. 4,345,328 to Gary D. White; U.S. Pat. No. 4,077,028 to Albert S. Lui and Majid Arbab; U.S. Pat. No. 4,319,356 to James E. Kocol and D. B. Schuck; U.S. Pat. No. 4,077,565 to Chester M. Nibby, Jr. and George J. Barlow; and U.S. Pat. No. 4,319,357 to Douglas C. Bossen.
The foregoing identified patents describe various types of systems that can code data bits with redundant check bits in various configurations, with check bits being recorded in the memory system with the data bits. When the data bits are to be accessed, systems are described for reconstituting check bits from the data bits read, and thereafter performing comparison to the check bits that were originally recorded. Syndrome bits are generated as a result of comparison of the reconstituted check bits to the check bits ready from memory. The syndrome bits are decoded and a determination made as to which, if any, error bits are detected, and which error bit(s) can be corrected. Various types of circuitry are described for effecting the corrections that can be accomodated in the system. It is noted, that the ECC systems and the parity systems all relate to evaluation of the data and associated control signals. Clearly these are important functions and provide assurance of data integrity.
In addition to the error detection and correction functions it has developed that through-checking is desirable for detecting and isolating errors that occur as data is transferred through the system. Through-checking ECC systems for use with memory devices are described in the identified co-pending applications entitled "MEMORY THROUGH-CHECKING SYSTEM", and "READ ERROR OCCURRENCE DETECTOR FOR ERROR CHECKING AND CORRECTING SYSTEM". Systems of this type relate to the accuracy of generation of the ECC signals, and the accuracy of operation of the circuitry, as distinguished from the accuracy of the data as manipulated.
In systems that utilize a multiplicity of processors to access, a common memory system, either for reading or writing, it has been found necessary to establish an access priority sequence between processors seeking access to the memory system. Memory systems that can accommodate multiple requestors, such as multiple processing units, are designated multiple port or multiple channel memory systems. In such systems, it is necessary to identify the processor seeking access to the memory system, and to enable the appropriate port or channel associated with the identified requestor. With multiple requestors, it is common to have requests queued up and to have memory addressing and data to be written available from the queued sources. In the event of a decoding error, that is an error in identifying the proper requestor, an entirely erroneous selection of addressing and data to be written can occur. Even assuming that parity is associated with the data words, or an ECC system is incorporated, such decoding errors will often go undetected because the word or words processed in the run stream will be proper and correct, but will be associated with the erroneously identified requestor. Since the requests are queued, the memory system is essentially pipelined and is conditioned to handle requests in a predetermined manner. Further, through timing control, the operation of the selection and memory system is overlapped. This means that certain functions related with one requestor are being completed while other functions of the next subsequent requestor are being initiated. It is clear that errors in decoding, that is erroneous identification of requestors, results in system malfunction that is difficult to isolate and identify if not detected close in time to the occurrence of the error condition.